1. Field of the Invention
The present invention relates to a configuration of a MOS transistor fabricated on a polycrystalline silicon substrate and a method of manufacturing the same. The present invention can be applied to MOS transistors that form an integrated circuit.
The present invention further relates to an SOI (silicon-on-insulator) structure which is a structure for forming single crystalline silicon on an insulator and a technique to provide the same structure.
More particularly, the present invention relates to a method of fabricating a single crystalline silicon layer referred to as "SIMOX" (separation-by-implanted oxygen) and a method of manufacturing a semiconductor device (e.g., transistor) utilizing such a silicon layer.
2. Description of the Related Art
(A) Techniques for forming various integrated circuits (generally referred to as ICs) utilizing single crystalline silicon substrates are known. Such techniques include a technique for forming a MOS transistor utilizing a single crystalline silicon substrate.
FIG. 23 is a schematic sectional view of a typical MOS transistor. FIG. 23 shows a section taken in the direction of the width of the channel. FIG. 23 does not show the source and drain regions. The source and drain regions are assumed to exist on this side of the plane of the drawing and on the other side of the same, respectively. It is therefore assumed that, in operation, carriers move from this side of the plane of the drawing to the other side or in the opposite way.
FIG. 23 shows a P-type silicon substrate 1 serving as a base (a common single crystalline silicon wafer is used). MOS semiconductor devices and other devices such as resistors, capacitors and active devices (not shown) are formed using this single crystalline silicon substrate 1.
A reference numeral 5 designates a field oxide film produced using LOCOS (local oxidation of silicon). The field oxide film 5 provides separation of devices. Therefore, the field oxide film 5 can be regarded as an oxide film for device separation.
A reference numeral 6 designates a gate electrode. The gate electrode 6 faces the single crystalline silicon substrate 1 with a gate oxide film 4 interposed therebetween. A region 3 of the single crystal silicon substrate 1 that faces the gate electrode 6 serves as a channel region. FIG. 23 shows an example of an N-channel type MOS transistor having an N-type channel.
A reference numeral 2 designates a region doped to have P.sup.+ -type properties, i.e., a region that exhibits P-type properties stronger than that of the substrate 1. This region is provided in order to prevent the formation of a parasitic channel (undesired expansion of the channel in the direction of the width thereof).
A parasitic channel can establish an unintended path for carrier movement, thereby causing abnormal operations and malfunctions.
Although the P.sup.+ -type region (an N.sup.+ -type region if the channel is a P-type channel) 2 is effective in preventing the formation of a parasitic channel, it results in a problem in that the diffusion of heavily doped impurities that provide P-type properties (B (boron) and As (arsenide) are commonly used) in the channel puts a limit on the effective channel width. This results in a phenomenon referred to as "narrow channel effect".
The narrow channel effect increases the threshold voltage. Further, it ruins the linearity be the relationship between the channel conductance and the gate voltage. This results in a problem in that a clear threshold voltage can not be defined.
Such a phenomenon adversely affects the overall device designing. This problem is more serious, the smaller the design rule is.
(B) A technique referred to as "SIMOX (separation-by-implanted oxygen)" as been known as one of SOI (silicon-on-insulator) structures (structures in which single crystalline silicon is formed on an insulator). (See Tadao Shimura, "SEMICONDUCTOR SILICON CRYSTAL ENGINEERING", Maruzen K. K. p. 217, Sep. 30, 1993.)
This is a technique for forming a single crystalline silicon layer on a buried oxide layer through steps of:
(1) implanting oxygen ions of a high concentration into the single crystalline silicon substrate in a dose of about 10.sup.18 /cm.sup.2 or more; and PA1 (2) performing thermal annealing to cause the oxygen implanted at the step (1) to react with the silicon in the single crystalline silicon substrate, thereby forming a buried oxide layer (a layer constituted by a silicon oxide film) in the single crystalline silicon substrate. PA1 (1) An integrated circuit can be obtained in which a complete level of two-dimensional separation of devices can be achieved. PA1 (2) Any parasitic capacitance between the devices and the substrate can be significantly reduced to allow the devices to operated at a higher speed. Further, it is possible to reduce crosstalk between the devices or between the devices and the wiring caused by parasitic capacitance through the substrate. PA1 (3) Devices can be arranged in an three-dimensional arrangement. PA1 (1) performing a thermal process at a temperature as high as 1300.degree. C. or more; and PA1 (2) implanting oxygen ions in separate steps which are each accompanied by a thermal process at a high temperature (see the above-mentioned "SEMICONDUCTOR SILICON CRYSTAL ENGINEERING"). PA1 forming a thermal oxidation film for device separation on the crystalline silicon substrate; and PA1 reducing defects at an interface between the thermal oxidation film and channel regions of the MOS semiconductors and in the vicinity thereof using an intentionally introduced metal element for promoting the crystallization of silicon at a heating process in an oxidizing atmosphere including a halogen element. PA1 intentionally introducing a metal element for promoting the crystallization of silicon; and PA1 forming a thermal oxidation film for device separation by means of a heating process in an oxidizing atmosphere including a halogen element. PA1 forming a thermal oxidation film for device separation; PA1 intentionally introducing a metal element for promoting the crystallization of silicon; and PA1 performing a heating process in an oxidizing atmosphere including a halogen element. PA1 intentionally adding nickel in the silicon substrate when the single crystalline silicon layer is formed; and PA1 intentionally removing the nickel. PA1 intentionally adding a metal element for promoting the crystallization of silicon in the silicon substrate when the single crystalline silicon layer is formed; and PA1 intentionally removing the metal element. PA1 intentionally introducing nickel when the single crystalline silicon layer is formed; and PA1 removing the intentionally introduced nickel by means of thermal oxidization. PA1 intentionally introducing a metal element for promoting the crystallization of silicon when the single crystalline silicon layer is formed; and PA1 removing the intentionally introduced metal element by means of thermal oxidization. PA1 doping a crystalline silicon substrate with oxygen; PA1 keeping nickel in contact with a surface of the crystalline silicon substrate; PA1 forming a silicon oxide layer in the crystalline silicon substrate by means of a heating process; PA1 forming a thermal oxidation layer on the surface of the crystalline silicon substrate; and PA1 removing the thermal oxidation layer, wherein PA1 a single crystalline silicon layer is obtained on the silicon oxide layer. PA1 doping a crystalline silicon substrate with oxygen; PA1 forming a silicon oxide layer in the crystalline silicon substrate by means of a heating process; PA1 keeping nickel in contact with a surface of the crystalline silicon substrate; PA1 forming a thermal oxidation layer on the surface of the crystalline silicon substrate; and PA1 removing the thermal oxidation layer, wherein PA1 a single crystalline silicon layer is obtained on the silicon oxide layer. PA1 keeping nickel in contact with a surface of the crystalline silicon substrate; PA1 doping a crystalline silicon substrate with oxygen; PA1 forming a silicon oxide layer in the crystalline silicon substrate by means of a heating process and, at the same time, PA1 forming a thermal oxidation layer on the surface of the crystalline silicon substrate; and PA1 removing the thermal oxidation layer, wherein PA1 a single crystalline silicon layer is obtained on the silicon oxide layer. PA1 doping a crystalline silicon substrate with oxygen; PA1 keeping a metal element for promoting the crystallization of silicon in contact with a surface of the crystalline silicon substrate; PA1 forming a silicon oxide layer in the crystalline silicon substrate by means of a heating process and, at the same time, forming a thermal oxidation layer on the surface of the crystalline silicon substrate; and PA1 removing the thermal oxidation layer, wherein PA1 a single crystalline silicon layer is obtained on the silicon oxide layer. PA1 doping a crystalline silicon substrate with oxygen; PA1 keeping a metal element for promoting the crystallization of silicon in contact with a surface of the crystalline silicon substrate; PA1 forming a silicon oxide layer in the crystalline silicon substrate by means of a heating process; PA1 forming a thermal oxidation layer on the surface of the crystalline silicon substrate; and PA1 removing the thermal oxidation layer, wherein PA1 a single crystalline silicon layer is obtained on the silicon oxide layer. PA1 doping a crystalline silicon substrate with oxygen; PA1 forming a silicon oxide layer in the crystalline silicon substrate by means of a heating process; PA1 keeping a metal element for promoting the crystallization of silicon in contact with a surface of the crystalline silicon substrate; PA1 forming a thermal oxidation layer on the surface of the crystalline silicon substrate; and PA1 removing the thermal oxidation layer, wherein PA1 a single crystalline silicon layer is obtained on the silicon oxide layer. PA1 keeping a metal element for promoting the crystallization of silicon in contact with a surface of a crystalline silicon substrate; PA1 doping the crystalline silicon substrate with oxygen; PA1 forming a silicon oxide layer in the crystalline silicon substrate by means of a heating process and, at the same time, forming a thermal oxidation layer on the surface of the crystalline silicon substrate; and PA1 removing the thermal oxidation layer, wherein PA1 a single crystalline silicon layer is obtained on the silicon oxide layer. PA1 doping a crystalline silicon substrate with oxygen; PA1 keeping a metal element for promoting the crystallization of silicon in contact with a surface of the crystalline silicon substrate; PA1 forming a silicon oxide layer in the crystalline silicon substrate by means of a heating process and, at the same time, forming a thermal oxidation layer on the surface of the crystalline silicon substrate; and PA1 removing the thermal oxidation layer, wherein PA1 a single crystalline silicon layer is obtained on the silicon oxide layer. PA1 a silicon oxide layer formed in a crystalline silicon substrate and a single crystalline silicon layer formed on the silicon oxide layer; PA1 an active layer for at least one device formed utilizing the single crystalline silicon layer; and PA1 a metal element present in the active layer with a distribution of concentration in which the concentration increases toward the interface opposite to the silicon oxide layer. PA1 an active layer for at least one device is formed utilizing the single crystalline silicon layer; and PA1 a metal element is present in the active layer with a distribution of concentration in which the concentration increases toward the interface opposite to the silicon oxide layer. PA1 forming a silicon oxide layer in a crystalline silicon substrate or on a surface thereof such that it is adjacent to a single crystalline silicon layer; PA1 intentionally introducing nickel before the formation of the silicon oxide layer; and PA1 intentionally removing the nickel during or after the formation of the silicon oxide layer. PA1 forming a silicon oxide layer in a crystalline silicon substrate or on a surface thereof such that it is adjacent to a single crystalline silicon layer; PA1 intentionally introducing a metal element for promoting the crystallization of silicon before the formation of the silicon oxide layer; and PA1 intentionally removing the metal element during or after the formation of the silicon oxide layer. PA1 doping a single crystalline silicon substrate 401 with oxygen (FIG. 10A); PA1 keeping nickel in contact with a surface of the single crystalline silicon substrate (FIG. 10B); PA1 forming a silicon oxide layer 404 in the single crystalline silicon substrate by means of a heating process (FIG. 10C); PA1 forming a thermal oxidation layer 407 on the surface of the single crystalline silicon substrate (FIG. 10D); and PA1 removing the thermal oxidation layer (FIG. 10E), wherein PA1 a single crystalline silicon layer 408 is obtained on the silicon oxide layer 405.
An electronic device fabricated utilizing a single crystalline silicon layer obtained using the above-described SIMOX technique has the following advantages.
(A) A possible technique for suppressing the above-described narrow channel effect in the conventional MOS semiconductor device shown in FIG. 23 is not to form the P.sup.+ region 2 therein. As mentioned above, however, the P.sup.+ region 2 has a function of suppressing the formation of a parasitic channel. Therefore, the omission of this region will result in significant problems associated with the formation of a parasitic channel.
It is an object of the present invention to provide a technique for obtaining a MOS transistor in which no parasitic channel of formed on the sides of the channel region without forming a P.sup.+ region 2 (N.sup.+ region if the channel is P-type).
(B) The SIMOX technique has problems as described below.
First, during an oxidizing reaction from which a buried oxide layer is formed, defects are formed in the vicinity of the interface between the buried oxide layer and single crystalline silicon layer (substrate) thereunder and in the vicinity of the interface between the buried layer and a single crystalline silicon layer thereon (which is used as the active layer of the device).
Such defects result from imperfect bonding of interstitial atoms (excess atoms interpenetrating lattices) and silicon atoms. They also originate from dislocation and the like.
Methods of reducing such defects include:
However, such methods have problems in that they require a high processing temperature and in that they result in complicated steps. Especially, a high temperature process puts a heavy burden on devices and it not preferable from the viewpoint of productivity.
It is an object of the present invention to solve the above-described problem with the technique of forming a single crystalline silicon layer utilizing SIMOX. In other words, it is an object of the present invention to provide a technique for forming a single crystalline silicon layer having a low defect density.
It is another object of the present invention to provide a device capable of high speed operations and having high reliability taking advantage of the above-described technique. It is still another object of the invention to solve the above-described problem without the need for a complicated process or a process at a high temperature.
It is a further object of the present invention to provide a technique for suppressing the effect of defects which are generally formed in a high density at an interface between a silicon oxide layer and a single crystalline silicon layer formed in contact with each other.